1. Field of the Invention
The present invention generally relates to address translation, and particularly relates to translating virtual addresses that create memory page boundary crossing conditions.
2. Relevant Background
Virtual memory is a memory management technique whereby possibly non-contiguous physical memory (physical address space) is presented to a process (software) as contiguous memory (virtual address space). Even though allocated physical memory is not always sequentially organized (or even in the same media, e.g., SDRAM and ROM), processes view memory as a linear sequence because they deal with a contiguous virtual address space. Further, programs are not usually aware of how physical memory is allocated. Instead, a processor or other device conventionally manages virtual memory allocation.
Memory management divides physical memory into pages (or segments) and provides a mapping of virtual addresses onto the actual physical memory pages which is transparent to processes accessing the memory. Processes view only the virtual address space while the physical address space is where corresponding data actually reside in memory. A processor conventionally maps the virtual address space onto a physical address space using address translation. Address translation involves looking up a physical address based on a given virtual address. A virtual address is conventionally divided into at least two parts—a virtual page number and a page offset. The virtual page number identifies a particular page of virtual memory. The page offset identifies a desired region (or block) within the page.
A page table maintained in main memory conventionally stores a list of virtual page numbers and corresponding physical page numbers. The page table is searched using the virtual page number portion of a virtual address. If a virtual page number matches an entry in the page table, the corresponding physical page number is retrieved from the table. Otherwise, a page table error occurs. The retrieved physical page number, along with the page offset, forms a physical address used to retrieve information from memory. The page number identifies the proper page of physical memory. The desired memory region within the page is then accessed using the page offset.
To improve performance, frequently accessed page table entries are stored locally to a processor, e.g., in a Translation Lookaside Buffer (TLB). TLBs may support a single level of local cache memory or multiple cache levels, e.g., level one instruction and data caches and a level two cache. In any event, a TLB performs address translation much the same way as a page table does. If a match occurs during a TLB lookup using a virtual page number, the corresponding physical page number is retrieved from the TLB and provided, with the page offset, to a physically-tagged cache. If the physical address hits in the cache, the cache line corresponding to the physical address is retrieved from the cache. Otherwise, a higher level cache lookup may occur.
Virtual memory enables programs to execute without requiring their entire address space to be resident in physical memory. Thus, programs can be executed using less physical memory than actually needed. In addition, virtual memory isolates programs from each other because each program's virtual address space can be independently mapped to one or more pages of physical memory allocated exclusively to that program. Also, application programs are simplified in that they are not responsible for memory management. However, certain types of memory accesses require additional address translation processing to complete successfully.
For example, when a misaligned memory access occurs, the desired word is located partly in one memory row and partly in another. If the two rows are allocated to different memory pages, a page boundary crossing occurs. An instruction that references a region in memory crossing a boundary between two memory pages is conventionally replicated and executed in two parts. A first page piece of the replicated instruction completes execution based on a physical address associated with the first memory page and a second page piece of the replicated instruction completes execution based on an address associated with the second memory page. Thus, the different memory pages are accessed separately by replicating the instruction.
Multiple address translations are conventionally required to obtain the physical memory addresses associated with the different memory pages. A first address translation is performed to retrieve the physical address associated with the first memory page and a second address translation is performed to retrieve the physical address associated with the second memory page. The additional address translation processing required for an instruction that creates a boundary crossing condition reduces processor performance and increases power consumption, particularly if access to a page table maintained in main memory is needed.